Semiconductor device and method of manufacturing semiconductor device

ABSTRACT

A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/183,471, filed Jul. 31, 2008, which claims priority of JapanesePatent Application No. 2007-200868, filed Aug. 1, 2007, the entirecontents of each of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method ofmanufacturing the semiconductor device. More particularly, the presentinvention relates to a semiconductor device having a vertical surroundgate transistor (SGT) structure and a method of manufacturing thesemiconductor device.

2. Description of Related Art

In recent years, semiconductor technology has been applied over a widerange. High integration and low power consumption are strongly requestedin integrated circuits from a general electronic equipment such as adynamic random access memory (DRAM) and a central processing unit (CPU)to a special purpose for an automotive engine control and a universalsatellite. In order to realize drastic high integration forsemiconductor integrated circuits, there has been expected anew-structure transistor alternative to a conventional planar-type metaloxide semiconductor (MOS) transistor.

As an example of the new-structure transistor, there has been known adevice using a silicon on insulator (SOI) wafer instead of aconventional silicon wafer. As shown in FIG. 11, a complementary MOS(SOI-CMOS) transistor 101 is formed on an SOI wafer 102. The wafer 102includes a single crystal silicon wafer 102 a, an embedded oxide film102 b, and a silicon layer 102 c that are sequentially stacked therein.Here, the SOI-CMOS transistor 101 comprises a source region 103 and adrain region 104 formed in the silicon layer 102 c, a body region 105arranged between the source region 103 and the drain region 104, a gateinsulating film 106 made from silicon oxide formed on the body region105, and a gate electrode 107 made from poly-silicon formed on the gateinsulating film 106. The source region 103 and the drain region 104 areimpurity-diffused regions that are formed by ion-implanting n-typeimpurities in the silicon layer 102 c. On the other hand, the bodyregion 105 is an impurity-diffused region that is formed byion-implanting p-type impurities in the silicon layer 102 c. Side walls108 made from silicon nitride are formed on both sides of the gateelectrode 107. Furthermore, an interlayer insulation film 109 made fromsilicon oxide is stacked so as to cover the gate electrode 107 and thesilicon layer 102 c. Contact plugs 110 a, 110 b, and 110 c arerespectively connected to the gate electrode 107, the source region 103,and the drain region 104, and are formed in the interlayer insulationfilm 109.

According to the above SOI-CMOS transistor, the silicon layer 102 chaving an impurity-diffused region such as the body region 105 isinsulated by the embedded oxide film 102 b from the silicon wafer 102 a.According to this, reduction of parasitic capacitance, prevention oflatch-up, reduction of junction leakage, and suppression of shortchannel effect are accomplished. However, the SOI wafer is expensivecompared to the conventional single crystal silicon wafer. For thisreason, it is required for a transistor that uses the conventionalsingle crystal silicon wafer to have the same characteristic as that ofthe SOI-CMOS transistor. The SOI wafer has a problem in that aself-heating effect occurs because thermal conductivities of theembedded oxide film and the silicon layer are largely different.Therefore, there is required a transistor in which heat generated byitself is effectively released similar to a conventional substrate.Furthermore, there is required a structure that can be applied to afloating-body-type transistor or the like that is used for a memory cellof capacitorless DRAM by making a design technique of a conventionaltransistor exploit. This structure can separate a substrate region and abody region so that many holes made by impact ionization can accumulate.However, manufacture of this structure has a problem in that it isdifficult to dope by a conventional ion implantation.

Moreover, a planar-type MOS transistor having a conventional structureis improved according to the development of new materials for a high-kgate insulating film, a metal gate electrode, and so on. However, with arequest of high integration for integrated circuits, a gate length hasbeen reduced year by year. Within the next 20 years, it is thought thatthis integration necessarily reaches a limit. There is requireddevelopment of mass production techniques to hold or improve ON currentswith keeping Moore's law for a future. For this purpose, there is neededa structure that improves strict control for a distribution of dopantand control for a gate. For that purpose, it is necessary to form asource region, a drain region, and a body region that are obtained bycontrolling the distribution of dopant in a nanometer scale and strictlydivide the regions.

On the other hand, if the body region has a channel formed therein,electric currents can not be controlled using only the small gateregion. For this reason, a short channel effect occurs. It is necessaryto guarantee a large gate region to form a channel in the whole siliconbody region. Then, it is necessary to control electric currents andrestrain a short channel effect. However, a planar-type transistor thatis a conventional all-around gate transistor has complicatedmanufacturing processes.

On the other hand, as a vertical all-around gate transistor capable thatis easily manufactured, there is developed a surround gate transistor(SGT) having a structure which is obtained by winding a gate insulatingfilm and a gate electrode around a silicon pillar including source anddrain regions and a channel region (refer to Japanese Unexamined PatentApplication, First Publication No. H06-21467, No. H06-244419, No.H09-8290, No. 2005-64031, No. 2005-197704 and No. 2003-229494).

As shown in FIG. 12, a conventional SGT transistor 201 has a siliconlayer 203 having a cylinder (pillar) shape, source and drain regions 204a and 204 b positioned at upper and lower portions thereof, and a bodyregion 205 positioned between the source and drain regions 204 a and 204b. The SGT transistor 201 further has a gate insulating film 206 thatcovers the body region 205 around the silicon layer 203 and a gateelectrode 207 via the gate insulating film 206. The source and drainregions 204 a and 204 b are impurity-diffused regions that are formed byion-implanting n-type impurities in the silicon layer 203. On the otherhand, the body region 205 is an impurity-diffused region that is formedby ion-implanting p-type impurities in the silicon layer 203.

However, a diameter of the silicon pillar must be increased tosufficiently guarantee the channel in the body region, in order toincrease ON currents in the structure of such SGT transistor 201. Forthis reason, an increase efficiency of ON currents per unit area is low.Further, it becomes a problem that a threshold voltage changes becausethe diameter of silicon pillar becomes wide as a result.

Moreover, as the other transistor, a fin-type field effect transistor(Fin FET) has been known. In order to improve ON currents in the FinFET, the silicon layer forming the channel must be thicker or beincreased in a lateral direction. Therefore, Fin FET has a disadvantagein an area efficiency in the case of combination with or substitution ofa conventional planar-type transistor. Moreover, when manufacturing atransistor with an ultrashort channel length, it is disadvantageous toform the ultrashort channel length because conventional ion-implantationprocesses are used. Since the shape of the transistor becomes higher ina direction perpendicular to the substrate or becomes longer in adirection of the substrate, the Fin FET has an unbalanced shape in whichan original feature of the Fin FET cannot be utilized. For this reason,there is a problem in that it is difficult to manufacture itself.

Therefore, a double-gate transistor having a structure of a verticaltransistor has been developed. The double-gate transistor has astructure by which leakage currents can be restrained when turning offthe transistor by controlling the electric currents with two gates.

However, in the vertical double-gate transistor, its channel width mustbe lengthened to improve ON currents. For that purpose, gate electrodesmust be arranged on both sides of the silicon layer forming the channelso as to sandwich the silicon layer. For this reason, there is a problemin that an occupied area per unit wafer area of the transistor becomeslarge.

SUMMARY

The present invention seeks to solve one or more of the above problems,or to improve those problems at least in part.

The present invention has been achieved in view of the situation above,and the object is to provide a semiconductor device having a surroundgate transistor with junction (SGTJ) structure of the verticaldouble-gate transistor by which a channel length can be ultrashort, andthus ON currents can be increased without changing the threshold valueby holding a silicon layer thickness constant and further the thresholdvalue can also be dynamically changed by a back gate. The presentinvention also provides a method for manufacturing the abovesemiconductor device.

The semiconductor device according to an embodiment of the presentinvention has the SGTJ structure in which one of two gate electrodes hasa pillar shape and is embedded in the center of a main pillar. In thisway, since small electrodes can be formed and thus the channel lengthcan be ultrashort, ON currents can be improved without changing thethreshold value while reducing the occupied area per unit wafer area.

Further, the embodiment of the present invention provides a transistorequal to that using an SOI substrate, which can realize the reduction ofparasitic capacitance, the prevention of latch-up, the reduction ofjunction leakage, and the suppression of short channel effect at lowcost without using the SOI substrate.

In one embodiment, there is provided a semiconductor device thatcomprises: a cylindrical main pillar that is formed on a substrate;source and drain diffused layers that are formed in a concentric shapeat upper and lower portions of the main pillar and made from afirst-conduction-type material; a body layer that is formed at anintermediate portion of the main pillar sandwiched between the sourceand drain diffused layers and made from the first-conduction-typematerial; a front gate electrode that is formed on a outer surface ofthe main pillar while placing a gate insulating film therebetween; and aback gate electrode that is formed inside the main pillar and comes incontact with the source and drain diffused layers and the body layer.

In one embodiment, there is provided a method for manufacturing asemiconductor device, the method comprises: sequentially forming, on asubstrate, a first-conduction-type first semiconductor film that becomesan upper potion of source and drain layers, a first-conduction-typesecond semiconductor film that becomes a body layer including a channelregion, and a first-conduction-type third semiconductor film thatbecomes a lower portion of the source and drain layers; removing centralaxis portions of the third semiconductor film, the second semiconductorfilm, and the first semiconductor film to form a pillar-shaped holepenetrating from an upper portion of the third semiconductor film to alower portion of the first semiconductor film and forming a back gateelectrode made from a second-conduction-type material in the hole;patterning the third semiconductor film, the second semiconductor film,and a part of the first semiconductor film to form a shape of which across section is substantially convex and form a concentric shape with afocus on a central axis when seeing a surface of the substrate fromabove, and thus forming a cylindrical main pillar; forming a gateinsulating film to cover at least an outer surface of the body layer;and forming a front gate electrode at an outer circumferential portionof the body layer while placing the gate insulating film therebetween.

In one embodiment, there is provided a method for manufacturing asemiconductor device according to the present invention, the methodcomprises: sequentially forming, on a substrate, a first-conduction-typefirst semiconductor film that becomes an upper potion of source anddrain layers, a first-conduction-type second semiconductor film thatbecomes a body layer including a channel region, and afirst-conduction-type third semiconductor film that becomes a lowerportion of the source and drain layers; removing central axis portionsof the third semiconductor film, the second semiconductor film, and thefirst semiconductor film to form a pillar-shaped hole penetrating froman upper portion of the third semiconductor film to a lower portion ofthe first semiconductor film and forming a gate insulating film so as tocover at least an inner surface of the body layer in an inner surface ofthe hole; forming a front gate electrode at an inner circumferentialportion of the body layer while placing the gate insulating filmtherebetween; patterning the third semiconductor film, the secondsemiconductor film, and a part of the first semiconductor film to form ashape of which a cross section is substantially convex and form aconcentric shape with a focus on a central axis when seeing a surface ofthe substrate from above, and thus forming a cylindrical main pillar;and forming a back gate electrode made from a second-conduction-typematerial on an outer surface of the main pillar.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a perspective view showing a semiconductor device according toan embodiment of the present invention;

FIG. 2A is a cross-sectional view showing the semiconductor deviceaccording to the embodiment of the present invention, taken along anA-A′ line shown in FIG. 1;

FIG. 2B is a cross-sectional view showing the semiconductor deviceaccording to the embodiment of the present invention, taken along a B-B′line shown in FIG. 1;

FIG. 3 is a cross-sectional schematic view exemplary showing thesemiconductor device according to the embodiment of the presentinvention;

FIG. 4A is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 4B is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 4C is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 5A is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 5B is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 6A is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 6B is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 6C is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 7A is a cross-sectional view explaining a method for manufacturingthe semiconductor device according to the embodiment of the presentinvention;

FIG. 7B is a cross-sectional view drawing explaining a method formanufacturing the semiconductor device according to the embodiment ofthe present invention;

FIG. 8 shows a substantial part of the semiconductor device according tothe embodiment of the present invention;

FIG. 9 shows a substantial part of the semiconductor device according tothe embodiment of the present invention;

FIG. 10 is a graph showing relation between voltages between a back gateand a drain and electric currents between the drain and a source whenchanging an inside gate voltage of the semiconductor device according tothe embodiment of the present invention;

FIG. 11 is a cross-sectional schematic view showing a conventionalsemiconductor device;

FIG. 12 is a perspective view showing the conventional semiconductordevice;

FIG. 13A is a cross-sectional view showing the conventionalsemiconductor device, taken along a C-C′ line shown in FIG. 12; and

FIG. 13B is a cross-sectional view showing the conventionalsemiconductor device, taken along a D-D′ line shown in FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

The invention will be described herein with reference to illustrativeembodiments. Those skilled in the art will recognize that manyalternative embodiments can be accomplished using the teachings of thepresent invention and that the invention is not limited to theembodiments illustrated here for explanatory purposes.

In addition, the drawings to be referred to in the followingdescriptions are views to explain the semiconductor device of thepresent embodiment, and therefore the magnitude such as the size or thethickness of each portion illustrated may be different from that of eachportion of a real semiconductor device.

[Basic Example of Semiconductor Device]

It will be described about a basic example of the semiconductor deviceof the present embodiment with reference to FIG. 1, FIG. 2A, and FIG.2B. FIG. 1 shows a perspective view of a structure of a principal partof the semiconductor device (SGTJ transistor) according to the presentembodiment. Moreover, FIG. 2A shows a cross-sectional view taken alongan A-A′ line shown in FIG. 1 and viewed from a direction seeing asurface of a semiconductor substrate from above, and FIG. 2B shows across-sectional view taken along a B-B′ line shown in FIG. 1.

The semiconductor device 1 shown in FIG. 1 comprises a cylindrical mainpillar 3 that is formed on a substrate 2 and of which a central axis Mis perpendicular to the surface of the substrate 2, source and draindiffused layers 4 a and 4 b that are formed in a concentric shapecentered on the central axis M at upper and lower portions of the mainpillar 3 and made from a first-conduction-type material, a body layer 5(see FIGS. 2A and 2B) that is formed at an intermediate portion of themain pillar 3 sandwiched between the source and drain diffused layers 4a and 4 b and made from the first-conduction-type material, a front gateelectrode 7 that is formed on an outer surface of the main pillar 3 tocover the body layer 5 while placing a gate insulating film 6therebetween, and a back gate electrode 8 that is connected with thesource and drain diffused layers 4 a and 4 b and the body layer 5 in ap-n junction manner while being formed in a pillar shape penetratingfrom the upper portion to the lower portion in an inner surface of themain pillar 3 and made from a second-conduction-type material.

By such a structure, an outside diameter can be increased while holdingthe same threshold voltage. For this reason, it is possible to realize avertical metal oxide semiconductor (MOS) transistor having a widechannel width in which ON currents can be improved.

A conventional planar-type MOS structure must set the dopingconcentration of a source, a drain, a lightly doped drain (LDD), apocket, and the body layer so that a threshold value is not changed inspite of the change of a channel length. However, in the vertical MOSstructure, the thickness of a silicon layer is also related to athreshold value. In order not to largely change the threshold value inspite of the change of the thickness of silicon layer, the thickness ofthe silicon layer must be held. For this reason, it is preferable tohave a structure in that the silicon layer forming a channel has acylindrical shape and a concentric shaped cross section.

On the other hand, an arbitrary threshold voltage in the same channellength can be realized by freely changing the thickness of siliconlayer. For this purpose, although a conventional ion implantation methodrequires a plurality of ion implantation processes, it can be realizedby a single etching manufacturing process in the semiconductor device ofthe present invention.

The back gate electrode 8 made from the second-conduction-type materialcan function like a back gate of a conventional double gate by applyinga reverse bias to the back gate electrode to change a threshold voltagewithout flowing an electric current even when a voltage is applied tobody layer 5. Thus, the threshold voltage can be dynamically raised orlowered. According to this, leakage currents when turning off thetransistor can be decreased. The source and drain diffused layers 4 aand 4 b and the body layer 5 of the transistor should be formed of thefirst-conduction-type material. The reason is that the transistorbecomes a bipolar transistor when the body layer 5 is formed of thesecond-conduction-type material different from the first-conduction-typematerial, and thus electric currents flow from the back gate electrode 8to the body layer 5.

The front gate electrode 7 is arranged at the outer side of the mainpillar 3, and the back gate electrode 8 is formed on the inner side ofthe main pillar 3 in a pillar shape penetrating from the upper portionto the lower portion. When this is done, since it is not necessary toprovide a gate oxide film on the inner side, it is possible to make aprecision of a manufacturing process easy. In general, it is necessarythat inside and outside gate oxide films have the same oxide filmthickness, in order to simultaneously operate the inside and outsidegates. However, an oxide film such as a thermal oxide film cannotrealistically have the same oxide film thickness from the reason ofthermal radiation. Therefore, it is suitable for the inside gate to havea structure by which the gate does not depend on the film thickness ofthe oxide film. For this reason, the inside and outside gates aremanufactured to have different structures, and thus an inside reversebias junction gate dynamically changes a threshold voltage. Then, gateoperations of a conventional transistor are performed by the outsidegate. In this way, a high speed and low power consumption transistor canbe made and be used as an improved SGT. As described above, it turns outthat the inside gate structure has margin width for a process and aprocess precision is suitable for a vertical transistor structure.

As shown in FIG. 2A and FIG. 2B, the layers (the source and draindiffused layers 4 a and 4 b and the body layer 5) of the main pillar 3are concentrically formed with a focus on the central axis M. In doingso, it is possible to realize a structure by which a transistor becomesa shape suitable for relaxation of an electric field and has channelwidth that can be easily increased. When this structure has a constantsilicon layer thickness in a state of constant doping concentration, anoutside diameter of a silicon cylinder, that is to say, a channel width,can be increased compared to the SGT structure while holding thethreshold voltage. Therefore, ON currents can be improved. When thesilicon layer forming the channel is formed in a concentricdoughnut-shaped silicon cylinder with a long channel width, an increaseefficiency of ON currents per unit wafer area is higher than that of ONcurrents of SGT. A conventional SGT structure has a complicated designin order to hold the same threshold voltage even if the silicon layerthickness and channel width are changed. For this reason, in order toobtain high ON currents per unit wafer area with keeping a goodtransistor characteristic, it is necessary to have a concentricdoughnut-shaped structure with a long channel width like thesemiconductor device of the present invention. Furthermore, high ONcurrents can be realized in the vertical metal oxide semiconductortransistor. As a result, this results in a transistor structure suitablefor a memory cell such as a phase change memory (PRAM) that requireslarge ON currents.

It is preferable that the body layer 5 also has the same concentricshape as that of the source and drain diffused layers 4 a and 4 b. It ispreferable that a surface of the body layer 5 is parallel to a p-njunction boundary between the back gate electrode 8 and the body layer5. In doing so, it is possible for the region (the body layer 5) formingthe channel to have a concentric shape, the gate width of the transistoris enlarged without enlarging an outline dimension, and ON currents areincreased.

Moreover, it is preferable that the layers (the source and draindiffused layers 4 a and 4 b and the body layer 5) of the main pillar 3have constant width in transverse sections thereof and have a constantheight in longitudinal sections thereof. In doing so, it is possible tohave a constant silicon layer thickness and a constant threshold voltageby a low doping concentration. Furthermore, since the outside diameterof the silicon cylinder can be increased while holding the constantsilicon layer thickness, ON currents can be improved. Moreover, it ispreferable that the gate insulating film 6 for covering the body layer 5to surround the body layer 5 also has a constant film thickness.

Further, it is preferable that the front gate electrode 7 for coveringthe gate insulating film 6 is also arranged to have the same heightposition and the same vertical length as those of the body layer 5 andis formed to have the same film thickness. A cross-sectional shapeviewed from the direction seeing the surface of the substrate 2 fromabove is not particularly limited. In addition to a circle as shown inFIG. 2A, the shape may be a triangle as shown in FIG. 8, or may be aquadrangle as shown in FIG. 9. Due to an influence of parasiticcapacitance or the like, the width of the front gate electrode 7parallel to the substrate 2 is also a factor which is important in viewof performance improvement. For this reason, it is important that thesource and drain diffused layers 4 a and 4 b protruding from the bodylayer 5 are largely separated from the front gate electrode 7.Therefore, it is preferable to lengthen the source and drain diffusedlayers 4 a and 4 b in the direction perpendicular to the substrate 2 andthus largely separate them from the front gate electrode 7.

A semiconductor device 51 shown in FIG. 8 comprises a main pillar 53that is formed on a substrate to have a central axis M1 perpendicular toa surface of the substrate and of which a cross-sectional shape is atriangle cylindrical shape when seeing the surface of the substrate fromabove, source and drain diffused layers 54 a and 54 b that are formed atupper and lower portions of the main pillar 53 in a concentric shapecentered on the central axis M1 and made from a first-conduction-typematerial; a body layer 55 that is formed at a central portion of themain pillar 53 sandwiched between the source and drain diffused layers54 a and 54 b and made from the first-conduction-type material; a frontgate electrode 57 that is formed to cover the body layer 55 on an outersurface of the main pillar 53 while placing a gate insulating film 56therebetween; and a back gate electrode 58 that is formed on an innersurface of the main pillar 53 in a pillar shape penetrating from theupper portion to the lower portion, is connected with the source anddrain diffused layers 54 a and 54 b and the body layer 55 in a p-njunction manner, and is made from a second-conduction-type material. Itis preferable that the body layer 55 has the same concentric shape asthat of the source and drain diffused layers 54 a and 54 b. It ispreferable that the body layer 55 has a constant width in a transversesection of the main pillar 53 surrounded by the front gate electrode 58and has a constant height in a longitudinal section thereof.Furthermore, it is preferable that the gate insulating film 56 also hasa constant film thickness.

A semiconductor device 61 shown in FIG. 9 comprises a main pillar 63that is formed on a substrate to have a central axis M2 perpendicular toa surface of the substrate and of which a cross-sectional shape is asquare cylindrical shape when seeing the surface of the substrate fromabove, source and drain diffused layers 64 a and 64 b that are formed atupper and lower portions of the main pillar 63 in a concentric shapecentered on the central axis M2 and made from a first-conduction-typematerial, a body layer 65 that is formed at a central portion of themain pillar 63 sandwiched between the source and drain diffused layers64 a and 64 b and made from the first-conduction-type material, a frontgate electrode 67 that is formed to cover the body layer 65 on an outersurface of the main pillar 63 while placing a gate insulating film 66therebetween, and a back gate electrode 68 that is formed on an innersurface of the main pillar 63 in a pillar shape penetrating from theupper portion to the lower portion, is connected with the source anddrain diffused layers 64 a and 64 b and the body layer 65 in a p-njunction manner, and made from a second-conduction-type material. It ispreferable that the body layer 65 has the same concentric shape as thatof the source and drain diffused layers 64 a and 64 b. It is preferablethat the body layer 65 has a constant width in a transverse section ofthe main pillar 63 surrounded by the front gate electrode 68 and has aconstant height in a longitudinal section thereof. Furthermore, it ispreferable that the gate insulating film 66 also has a constant filmthickness.

The source and drain diffused layers 4 a, 4 b, 54 a, 54 b, 64 a, and 64b and the body layers 5, 55, and 65 made from the first-conduction-typematerial may be n-type doped silicon, and the back gate electrodes 8,58, and 68 made from the second-conduction-type material may be p-typedoped silicon. On the other hand, the source and drain diffused layers 4a, 4 b, 54 a, 54 b, 64 a, and 64 b and the body layers 5, 55, and 65made from the first-conduction-type material may be, for example, p-typedoped silicon, and the back gate electrodes 8, 58, and 68 made from thesecond-conduction-type material may be, for example, n-type dopedsilicon.

In regard to the gate electrode, a plurality of gate electrodes may beprovided in a direction perpendicular to the surface of the body layers5, 55 and 65, and capacitance may be provided in source layers (thesource and drain diffused layers 4 a, 54 a, and 64 a) between the gateelectrodes. According to this, it is possible to realize a multivaluedDRAM which uses the plurality of gate electrodes from only one drainlayer (the source and drain diffused layers 4 b, 54 b, and 64 b).Further, the gate insulating films 6, 56, and 66 may be respectivelyformed on inner surfaces of the main pillars 3, 53, and 63, the frontgate electrodes 7, 57, and 67 may be respectively formed on the insidesthereof, and the back gate electrodes 8, 58, and 68 may be respectivelyformed on outer surfaces of the main pillars 3, 53, and 63, so as tohave a reverse function of the gate electrode.

[Example of Semiconductor Device]

FIG. 3 shows an example of a concrete configuration of the semiconductordevice 1 shown in FIG. 1, FIG. 2A, and FIG. 2B. A semiconductor device11 shown in FIG. 3 includes a cylindrical main pillar 18 that is formedon a substrate 12 to have a central axis M′ perpendicular to a surfaceof the substrate 12; a source layer 15 a and a drain layer 13 a that areformed at upper and lower portions of the main pillar 18 in a concentricshape centered on the central axis M′ and made from an n⁺-type(first-conduction-type) material; a body layer 14 a that is formed at acentral portion of the main pillar 18 sandwiched between the sourcelayer 15 a and the drain layer 13 a, and made from the n-type(first-conduction-type) material; a front gate electrode 20 that isformed on an outer surface of the main pillar 18 to cover the body layer14 a while placing a gate insulating film 19 therebetween; and a backgate electrode 17 that is formed on an inner surface of the main pillar18 in a pillar shape penetrating from the upper portion to the lowerportion, that is connected with the source layer 15 a, the drain layer13 a, and the body layer 14 a in a p-n junction manner, and that is madefrom a p-type (second-conduction-type) material. Drawn electrodeportions 13 c and 13 d drawing an electrode are formed to protrude fromthe lower portion of the drain layer 13 a to its outer circumferentialdirection. In this manner, since the lower and upper portions of thedrain layer 13 a are sufficiently separated, parasitic capacitance ofthe drain layer 13 a and the gate (body layer 14 a) can be largelyreduced and positioning of an electrode and a wire can be easilyperformed.

In this manner, since the drawn electrode portions 13 c and 13 d areformed, the drain layer 13 a can be formed to have a structure thatlargely protrudes in a transverse direction in comparison with the bodylayer 14 a and the source layer 15 a, and thus a poly-silicon wire canbe easily performed. At this time, the front gate electrode 20 made frompoly-silicon can be formed on a silicon oxide insulating layer thatfunctions as an etching stop layer (not shown). Due to an influence ofparasitic capacitance or the like, the width of the gate electrodeparallel to the substrate 12 is also the factor which is important toperformance improvement. For this reason, it is important to largelyseparate the source layer 15 a and the drain layer 13 a protruding fromthe body layer 14 a from the front gate electrode 20. In this manner,since the drawn electrode portions 13 c and 13 d are provided, the drainlayer 13 a can be lengthened in a direction perpendicular to thesubstrate 12 and thus be largely separated from the front gate electrode20.

The front gate electrode 20 made from poly-silicon can be formed on asilicon oxide insulating layer that functions as an etching stop layer(not shown). Due to an influence of parasitic capacitance or the like,the width of the front gate electrode 20 parallel to the substrate 12 isalso the factor which is important to performance improvement. For thisreason, it is important to largely separate the drain layer 13 a and thesource layer 15 a protruding from the body layer 14 a from the gateelectrode. In this manner, since the drawn electrode portions areprovided, the drain layer 13 a can be lengthened in a directionperpendicular to the substrate and be largely separated from the frontgate electrode 20.

An interlayer insulation film 21 is deposited on the entire surface ofthe substrate 12. A contact hole 22 a connected to the drain layer 13 ais formed at the outer side of the drawn electrode portion 13 d. Acontact hole 22 b connected to the source layer 15 a is formed on theupper portion of the source layer 15 a. A contact hole 22 c connected tothe front gate electrode 20 is symmetrically formed at the opposite sideof the contact hole 22 a so as to be contacted at the lateral face ofthe front gate electrode 20. A contact hole 22 d connected to the backgate electrode 17 is formed in the upper portion of the back gateelectrode 17. The contact holes 22 a, 22 b, 22 c, and 22 d includetherein poly-silicon that is amorphous silicon doped with n-type orp-type impurities (P and As, or B), and contact plugs 23 a, 23 b, 23 c,and 23 d are respectively formed in the contact holes. The contact holes22 a, 22 b, 22 c, and 22 d may include therein tungsten (W) instead ofthe poly-silicon, and the contact plugs 23 a, 23 b, 23 c, and 23 d maybe respectively formed in the contact holes. In addition, wires arerespectively connected to the contact plugs 23 a, 23 b, 23 c, and 23 d.Since the first wire (the contact plug 23 c) wired to the front gateelectrode 20 and the second wire (the contact plug 23 a) wired to thedrawn electrode portion 13 d are symmetrically arranged at the outerside of the main pillar 18, the parasitic capacitance can be reduced.Moreover, since the third wire (the contact plug 23 b) wired to thesource layer 15 a is formed at the upper side of the main pillar 18, thethird wire can be disposed at a position having small parasiticcapacitance or the like.

The layers of the main pillar 18 are formed in a concentric shape with afocus on the central axis M′, similarly to the semiconductor device 1shown in FIG. 2A and FIG. 2B. It is preferable that the body layer 14 aalso has the same concentric shape as that of the source layer 15 a andthe drain layer 13 a. It is preferable that the surface of the bodylayer 5 is parallel to the p-n junction boundary between the back gateelectrode 6 and the body layer 5. It is preferable that the layers ofthe main pillar 18 have a constant width in their transverse sectionsand have a constant height in their longitudinal sections. Moreover, itis preferable that the gate insulating film 19 covering the body layer14 a also has a constant film thickness. Further, it is preferable thatthe front gate electrode 20 covering the gate insulating film 19 isarranged to have the same height position and the same vertical lengthas those of the body layer 14 a and is formed to have the same filmthickness. In addition, although the above described embodiment isdescribed using a cylindrical transistor, an SGTJ transistor of thepresent invention is not limited to this shape. For example, as shown inFIG. 8 and FIG. 9, the SGTJ transistor can have a multi-angular pillarsuch as a square pillar or a triangle pillar of which thecross-sectional shape is a concentric quadrangle or triangular shape.However, it is preferable to have a constant width in the transversesection of the main pillar surrounded by the front gate electrode andhave a constant height in a longitudinal section thereof. Furthermore,it is preferable that the gate insulating film also has a constant filmthickness.

Moreover, in regard to a conduction type, the source layer 15 a, thedrain layer 13 a, and the body layer 14 a may be formed of p-typematerial, and the back gate electrode 17 may be formed of n-typematerial. Further, in regard to the gate electrode, a plurality of gateelectrodes may be provided in a direction perpendicular to the surfaceof the main pillar 18, and capacitance may be provided in the sourcelayers 15 a between the gate electrodes. In this way, it is possible torealize a multivalued DRAM which uses the plurality of gate electrodesfrom only the drain layer 13 a. Moreover, the gate insulating film 19may be formed on the inner surface of the main pillar 18, the front gateelectrode 20 may be further formed on inside thereof, and the back gateelectrode 17 may be formed on the outer surface of the main pillar 18,so as to have a reverse function of the gate electrode.

As described above, according to the semiconductor device 11 of theembodiment of the present invention, it is possible to realize acharacteristic equal to that of the SOI transistor at low cost withoutusing an expensive SOI wafer and realize a transistor which can performthe reduction of parasitic capacitance, the prevention of latch-up, thereduction of junction leakage, and the suppression of short channeleffect.

According to the semiconductor device 11, since the SOI substrate is notused, it is possible to solve a problem of the self-heating effect owingto the large difference between heat conductivities of the embeddedoxide film and the silicon layer. The semiconductor device 11 becomes avertical metal oxide semiconductor structure using a conventionalsubstrate which can effectively release heat generated by the transistorsimilarly to the conventional substrate. In addition to this, when thesemiconductor device is applied to a memory cell of DRAM, junctionleakage currents can be reduced and refresh frequency per time can bereduced.

Moreover, the semiconductor device becomes a transistor structure of aplanar-type transistor when the vertical metal oxide semiconductor has aheight similar to the height of the conventional planar-type gate. Shortchannel effect can be restrained like the Fin FET and SGT by surroundingthe whole channel region with the gate. A transistor with an extremelyshort channel can be manufactured by doping during the crystal growth incomparison with the manufacture by ion implantation. Moreover, thedesign of a transistor becomes easy because the derivation of adepletion layer width of a p-n junction in a design can be also computedby step-type approximation.

[Example of Manufacturing Method of Semiconductor Device]

Next, it will be explained about a manufacturing method of thesemiconductor device 11 shown in FIG. 3 with reference to FIG. 4A toFIG. 7B. This manufacturing method includes a process of sequentiallyforming a first semiconductor film, a second semiconductor film, and athird semiconductor film, which become each layer in the main pillar, onthe substrate; a process of forming the back gate electrode; a processof forming the main pillar by etching; a process of forming the gateinsulating film; and a process of forming the front gate electrode.

First, in the process of forming the first to the third semiconductorfilms, the single crystal silicon substrate 12 is prepared as shown inFIG. 4A, for example. Then, the surface 12 a of the substrate is cleanedin a surface cleaning manner (APM cleaning+SPM cleaning). After removinga natural oxide film and particles attached to the substrate surface 12a from the start, a natural oxide film is formed on the surface 12 a ofthe substrate. Next, as shown in FIG. 4B, the first semiconductor film13, the second semiconductor film 14, and the third semiconductor film15 are sequentially stacked. In a process of forming the first to thethird semiconductor films 13 to 15, a silicon film is formed and at thesame time an impurity which is a dopant element is introduced.

As set forth, in order to remove the natural oxide film of the surface12 a of the substrate, the substrate is heated to 1200 degrees Celsiusor more within a vacuum chamber so as to expose an atomic siliconsurface. Next, the semiconductor substrate 12 is heated to around 1100degrees Celsius that are crystal growth temperature of silicon. Then,single crystal silicon is grown by a chemical vapor deposition (CVD)method or the like, using SiH₄, SiH₂Cl₂, SiHCl₃, SiCl₄, and so on asprecursor gases. N-type impurities such as PH₃, AsH₃, and so on areintroduced so that doping concentration becomes from 1×10¹⁵ to 1×10²²cm⁻³. The n⁺-type first semiconductor film 13 is formed, and then then-type second semiconductor film 14 and the n⁺-type third semiconductorfilm 15 are sequentially stacked, where the n⁺-type means high-densityn-type.

Total thickness of the first to the third semiconductor films 13 to 15should be as thick as needed. For example, it is preferable that thetotal thickness is around 50 nm. According to this, since the distancebetween the drain region or the source region and the gate electrode isseparated, the parasitic capacitance becomes small.

Moreover, a molecular beam epitaxy (MBE) method or the like using asolid-state silicon source may be used in place of a CVD method. Even inthis case, P and As, or B, and the like are used as p-type or n-typeimpurities similarly to the above. In order to remove the native oxidefilm, an etching in a multi-chamber or the like except a heating chambermay be used.

In this manner, the doping method during the crystal growth can directlycontrol the type of dopant and the doping concentration unlike theconventional ion implantation. For this reason, since the type of dopantcan be instantly changed and the precise gradient of dopingconcentration can be freely set dynamically and continuously, design andmanufacture thereof are easy. The LDD, the pocket, and the body layerforming a channel can be designed by applying this characteristic. AnLDD layer reduces the doping concentration compared to the drain layerand the source layer, and is formed directly over the drain (source)layer and directly under the source (drain) layer. Moreover, it ispossible to continuously manufacture the LDD layer from the source layerand the drain layer. For this reason, when manufacturing the pocketlayer and the body layer forming the channel, the manufacture can beperformed by changing the type of dopant or by changing concentration.

As described above, the derivation of a depletion layer width of a p-njunction in a design can be also computed by step-type approximation.For this reason, it is possible to improve a trial manufacturing cost, adesign efficiency, and a yield. A vertical transistor in which doping isperformed during the crystal growth is the most suitable for design andmanufacture of a mass-production type and ultrashort channel typetransistor.

Next, in the process of forming the back gate electrode, central axisportions of the first to the third semiconductor films 13 to 15 areremoved as shown in FIG. 4C. The pillar-shaped hole 16 penetrating fromthe upper portion of the third semiconductor film 15 to the lowerportion of the first semiconductor film 13 is formed. Crystal growth ofp-type silicon or deposition of p-type poly-silicon is performed in thehole 16. Then, the back gate electrode 17 is formed. As set forth, atfirst, after coating a resist on the third semiconductor film 15,exposure is performed using a reticle. Then, a resist pattern is formedon the third semiconductor film 15. After that, anisotropic dry etchingis performed along this resist pattern. From the top, the thirdsemiconductor film 15 corresponding to the first layer and the secondsemiconductor film 14 corresponding to the second layer are removed, andthe first semiconductor film 13 corresponding to the third layer isfurther removed, so as to form the hole 16.

Alternatively, an oxide film that acts as a hard mask is formed on a topface of the third semiconductor film 15 as is thicker than the nativeoxide film, by annealing the third semiconductor film 15. Next, aftercoating the resist, exposure is performed using the reticle. Then, theresist pattern is formed on the hard mask layer. After that, the hardmask is formed by dry etching along this resist pattern. Finally,anisotropic wet etching is performed in tetra-methyl-ammonium-hydroxide(TMAH) that is an alkali solution. The third semiconductor film 15corresponding to the first layer and the second semiconductor film 14corresponding to the second layer are removed, and the firstsemiconductor film 13 corresponding to the third layer is furtherremoved, so as to form the hole 16.

Then, in order to form the back gate electrode 17, crystal growth ofp-type silicon or deposition of p-type poly-silicon is performed in thehole 16. P-type silicon crystal (or p-type poly-silicon) is grown untilit becomes thicker than the third semiconductor film 15, and then thesurface of p-type silicon crystal (or p-type poly-silicon) is planed bychemical mechanical polishing (CMP). Furthermore, p-type silicon crystal(or p-type poly-silicon) is etched back until it becomes slightlythinner than the third semiconductor film 15.

In this way, a reverse bias can be applied by forming the p-type backgate electrode 17. The semiconductor device of the present invention canfunction like a back gate of a conventional double gate by changing thethreshold voltage without flowing electric currents even when a voltageis applied to body layer. For this reason, it is possible to decreaseleakage currents when turning off the transistor by dynamically raisingor lowering the threshold voltage. However, it is necessary that thefirst to the third semiconductor films 13 to 15 that become the drainlayer, the body layer, the source layer of this transistor are formed ofan n-type semiconductor. The reason is that the transistor becomes abipolar transistor when the body layer is a p-type and thus electriccurrents flow from the back gate electrode to the body layer.

Moreover, since the back gate electrode 17 is formed in a pillar shapepenetrating from the upper portion to the lower portion on the innerside of the main pillar 18, a gate oxide film does not have to beprovided on the inner side. For this reason, it is possible to make aprecision of a manufacturing process easy. In general, the inside andoutside gate oxide films must have the same oxide film thickness, inorder to simultaneously operate internal and external gates. However,oxide films such as a thermal oxide film cannot realistically have thesame oxide film thickness because of the reason of thermal radiation.For this reason, it is preferable that the inside gate has a structurewhich does not depend on a film thickness of the oxide film. Here, whenthe inside reverse bias junction gate dynamically changes the thresholdvoltage and the outside gate operates like the gate of the conventionaltransistor in a state that the inside and outside gates have differentgate structures, a high speed and low power consumption transistor canbe realized as improved SGT. As described above, in the verticaltransistor structure, it is preferable to form an inside gate structurethat has a width in a process margin and can make a process precisioneasy.

Subsequently, in the process of forming the main pillar by etching, thethird semiconductor film 15, the second semiconductor film 14, and apart of the first semiconductor film 13 are patterned to form the firstto the third semiconductor films 13 to 15 in a shape of which a crosssection is substantially convex, as shown in FIG. 5A and FIG. 5B. Thecylindrical main pillar 18 is formed by shaping the films in aconcentric shape with a focus on the central axis M when seeing thesubstrate surface 12 a of the substrate 12 from above.

As set forth, at first, after coating the resist on the thirdsemiconductor film 15, the exposure is performed using the reticle.Then, the resist pattern is formed on the third semiconductor film 15.After that, anisotropic dry etching is performed along this resistpattern. From the top, the third semiconductor film 15 corresponding tothe first layer and the second semiconductor film 14 corresponding tothe second layer are removed, and the first semiconductor film 13corresponding to the third layer is further removed while leaving it atabout 10 nm.

Alternatively, the oxide film that acts as the hard mask is formed onthe top face of the third semiconductor film 15 as is thicker than anative oxide film, by annealing the third semiconductor film 15. Next,after coating the resist, the exposure is performed using the reticle.Then, the resist pattern is formed on the hard mask layer. After that,the hard mask is formed by dry etching along the resist pattern.Finally, anisotropic wet etching is performed in TMAH or the like thatis an alkali solution. The third semiconductor film 15 corresponding tothe first layer and the second semiconductor film 14 corresponding tothe second layer are removed, and the first semiconductor film 13corresponding to the third layer is further removed while leaving it atabout 10 nm.

Here, from the top, a remaining portion of the third semiconductor film15 corresponding to the first layer becomes the source layer (the upperportion of the source and drain diffused layers) 15 a, and a remainingportion of the second semiconductor film 14 becomes the body layer 14 a.Moreover, a concentric-shape portion in contact with the body layer 14 ain a remaining portion of the first semiconductor film 13 becomes thedrain layer (the lower portion of the source and drain diffused layers)13 a, so as to form the cylindrical main pillar 18.

In this manner, since the cylindrical main pillar 18 is formed, it ispossible to realize a vertical metal oxide semiconductor transistorhaving a long channel width that can increase an outside diameter whileholding a threshold voltage constant and can improve ON currents. In aconventional SGT structure, doping concentration of a source, a drain,LDD, pocket, and a body layer had to be set so that the threshold valuewas not changed even if the channel length was changed. However, sincethe thickness of a silicon layer also has influence on a threshold valuein case of the vertical MOS, the thickness of a silicon layer must beheld constant in order not to largely change the threshold valueirrespective of the change of the thickness of silicon layer. For thisreason, it is preferable that the silicon layer forming the channel is acylinder type and has a concentric cross section. On the contrary, anarbitrary threshold voltage in the same channel length can be realizedby freely changing the thickness of a silicon layer. For this purpose,although a conventional ion implantation method requires a plurality ofion implantation processes, it can be realized by a single etchingmanufacturing process in the semiconductor device of the presentinvention.

Moreover, the main pillar 18 has a constant width in a transversesection thereof and a constant height in a longitudinal section thereof.In this way, it is possible to hold the thickness of a silicon layerconstant with a low-concentration doping and hold a threshold voltageconstant. Further, since the outside diameter of the main pillar 18 canbe increased while holding the thickness of a silicon layer constant, ONcurrents can be improved.

Moreover, since the body layer 14 a has the same concentric shape asthat of the source layer 15 a and the drain layer 13 a, a region (thebody layer 14 a) in which the channel is formed becomes a concentricdoughnut-shape. It is possible to enlarge the gate width of thetransistor without enlarging an outline dimension and to increase ONcurrents.

Moreover, the layers (the source layer 15 a, the body layer 14 a, andthe drain layer 13 a) of the main pillar 18 are concentrically formedwith a focus on the central axis M′. In doing so, it is possible torealize a structure by which a transistor becomes a shape suitable forrelaxation of electric fields and has a channel width capable of beingeasily increased. Compared to the SGT structure, this structure canincrease the outside diameter of the silicon cylinder, that is to say,the channel can be increased width with keeping the threshold voltagebeing constant when the thickness of silicon layer and the dopingconcentration are constant. Therefore, ON currents can be improved. Whenthe silicon layer forming the channel is formed in a concentricdoughnut-shaped silicon cylinder with long channel width, increaseefficiency of ON currents per unit wafer area is higher than that of ONcurrents of SGT. A conventional SGT structure had a complicated designin order to hold the same threshold voltage even if the silicon layerthickness and the channel width were changed. For this reason, in orderto obtain high ON currents per unit wafer area while holding a goodtransistor characteristic, it is necessary to have a concentricdoughnut-shaped structure with the long channel width like thesemiconductor device of the present invention. Furthermore, high ONcurrents can be realized in the vertical metal oxide semiconductortransistor. As a result, this results in a transistor structure suitablefor a memory cell such as a phase change memory (PRAM) that requireslarge ON currents.

Subsequently, the drawn electrode portion is formed from an about 10 nmthin film 13 b at the side of the substrate 12 in the remaining portionof the first semiconductor film 13. The thin film 13 b is etched asshown in FIG. 6A. The drawn electrode portions 13 c and 13 d are formedto protrude from the lower portion of the drain layer 13 a to an outercircumferential direction, and an electrode is shaped in the drawnstructure. In this manner, since the lower portion and the upper portionof the drain layer 13 a are sufficiently separated, parasiticcapacitance of the drain layer 13 a and the gate can be largely reduced.At the same time, electrodes and wires can be easily positioned.

In this manner, since the drawn electrode portions 13 c and 13 d areformed, the drain layer 13 a can be formed to have a structure thatlargely protrudes in a transverse direction in comparison with the bodylayer 14 a and the source layer 15 a. Therefore, a poly-silicon wire canbe easily performed. At this time, the front gate electrode made frompoly-silicon can be formed on a silicon oxide insulating layer thatfunctions as an etching stop layer. From an influence of parasiticcapacitance or the like, the width of the gate electrode parallel to thesubstrate 12 is also the factor which is important to performanceimprovement. For this reason, it is important to largely separate thesource layer 15 a and the drain layer 13 a protruding from the bodylayer 14 a from the front gate electrode. In this manner, since thedrawn electrode portions 13 c and 13 d are provided, the drain layer 13a can be lengthened in a direction perpendicular to the substrate 12 andthus be largely separated from the front gate electrode.

Next, in the process of forming the gate insulating film, the gateinsulating film is formed on the outer surface of the main pillar 18 soas to at least cover the body layer 14 a. As set forth, as shown in FIG.6B, an oxide film with about 1 to 10 nm thickness is deposited on themain pillar 18 and the drawn electrode portions 13 c and 13 d, by suchas a CVD method or an annealing method in an oxidation atmosphere. Theannealing method in an oxidation atmosphere dry-oxidizes the surfaces ofthe main pillar 18 and the drawn electrode portions 13 c and 13 d in anoxidation furnace, in order to form the gate insulating film 19 madefrom silicon oxide film. In the CVD method, a high-k film such as HfO₂of high dielectric materials and insulating materials such as SiO₂ aredeposited using raw gas such as tetra-ethoxy-silane (TEOS).

Next, in the process of forming the front gate electrode, the front gateelectrode is formed to cover the body layer 14 a while placing the gateinsulating film 19 therebetween. As set forth, a poly-silicon layer isfirstly formed to cover the gate insulating film 19 by the CVD method.Then, after planing unevenness of the top face of the poly-silicon layerby CMP, the poly-silicon layer is etched back until the gate insulatingfilm 19 a formed on the top face of the main pillar 18 in the gateinsulating film 19 is exposed, as shown in FIG. 6C. Furthermore, thepoly-silicon layer is removed by etching so that outside portions of thegate insulating film 19 b in contact with the surface 12 a of thesubstrate and the gate insulating film 19 c formed on the drawnelectrode portions 13 c and 13 d are exposed, in order to form the frontgate electrode 20 made from the remaining portion of the poly-siliconlayer.

Subsequently, an interlayer insulation layer 21 made from a 25 to 40 nmor more oxide film is formed by the CVD method or the like, as shown inFIG. 7A. As set forth, the oxide film is deposited on the entire surfaceof the substrate 12 by the CVD method which uses a gas source of siliconoxide such as TEOS. Alternatively, a film may be formed by a method suchas spin on glass (SOG) using low-dielectric low-k materials. This oxidefilm functions as an interlayer insulation film between an individualdevice and a wire. In order to reduce an etching irregularity of thefollowing process, unevenness of the top face of the interlayerinsulation film 21 is removed and planed by CMP.

Next, as shown in FIG. 7B, the interlayer insulation film 21 is etchedand the contact hole 22 a connected to the drain layer 13 a is formed atthe outer side of the drawn electrode portion 13 d. The contact hole 22b connected to the source layer 15 a is formed on the upper portion ofthe source layer 15 a, and the contact hole 22 c connected to the frontgate electrode 20 is symmetrically formed at the side opposite to thecontact hole 22 a so as to contact in a lateral face of the front gateelectrode 20. The contact hole 22 d connected to the back gate electrode17 is formed on the upper portion of the back gate electrode 17. Next,by the CVD method, the contact holes 22 a, 22 b, 22 c, and 22 d includetherein poly-silicon that is amorphous silicon doped with p-type orn-type impurities (P, As and B), and the contact plugs 23 a, 23 b, 23 c,and 23 d are respectively formed in the contact holes. The contact holes22 a, 22 b, 22 c, and 22 d may include therein tungsten (W) instead ofthe poly-silicon, and the contact plugs 23 a, 23 b, 23 c, and 23 d maybe respectively formed in the contact holes. In addition, wires arerespectively connected to the contact plugs 23 a, 23 b, 23 c, and 23 d.Since the first wire (the contact plug 23 c) wired to the front gateelectrode 20 and the second wire (the contact plug 23 a) wired to thedrawn electrode portion 13 d are symmetrically arranged at the outerside of the main pillar 18, parasitic capacitance can be reduced.Moreover, since the third wire (the contact plug 23 b) wired to thesource layer 15 a is formed at the upper side of the main pillar 18, thethird wire can be disposed at a position having small parasiticcapacitance or the like. As described above, it is possible tomanufacture the semiconductor device 11 shown in FIG. 3.

In addition, although the above-described embodiment was described usinga cylindrical transistor, the SGTJ transistor of the present inventionis not limited to this shape. For example, as shown in FIG. 8 and FIG.9, the SGTJ transistor can have a multi-angular pillar such as a squarepillar or a triangle pillar of which the cross-sectional shape is aconcentric quadrangle or triangular shape. However, it is preferable tohave constant width in the transverse section of the main pillarsurrounded by the front gate electrode and have a constant height in itslongitudinal section. Furthermore, it is preferable that the filmthickness of the gate insulating film is also constant.

Moreover, in regard to conductivity type, the first to thirdsemiconductor films 13 to 15 may be formed of p-type material, and theback gate electrode 17 may be formed of n-type material. Further, inregard to the gate electrode, a plurality of gate electrodes may beprovided in a direction perpendicular to the outer surface of the mainpillar 18, and capacitance may be provided in the source layers 15 abetween the gate electrodes. In this way, it is possible to realize amultivalued DRAM which uses the plurality of gate electrodes from onlythe drain layer 13 a. Moreover, the gate insulating film 19 may beformed on the inner surface of the main pillar 18, the front gateelectrode 20 may be further formed on its inside, and the back gateelectrode 17 may be formed on the outer surface of the main pillar 18,so as to have a reverse function of the gate electrode.

According to the manufacturing method of the semiconductor device 11 asdescribed above, it is possible to realize a characteristic equal tothat of the SOI transistor at low cost without using an expensive SOIwafer and realize a transistor which can perform reduction of parasiticcapacitance, prevention of latch-up, reduction of junction leakage, andsuppression of short channel effect. Furthermore, since the SOIsubstrate is not used, it is possible to cancel a problem of aself-heating effect owing to the large difference between heatconductivity of the embedded oxide film and heat conductivity of thesilicon layer. The semiconductor device 11 becomes a vertical MOSstructure using a conventional substrate which can effectively releaseheat generated by the transistor similarly to the conventionalsubstrate. In addition to this, when the semiconductor device is appliedto a memory cell of DRAM, junction leakage currents can be reduced andrefresh frequency per time can be reduced. Moreover, the semiconductordevice becomes a planar-type transistor when the vertical MOS has aheight similar to the height of the conventional planar-type gate. Shortchannel effect can be restrained like Fin FET and SGT by surrounding thewhole channel region with the gate. A transistor with an extremely shortchannel can be manufactured by dopant implantation in crystal growth incomparison with the manufacture by ion implantation. Moreover, a designof a transistor becomes easy because the derivation of a depletion layerwidth of a p-n junction in a design can be also computed by step-typeapproximation.

Embodiment

Next, it will be explained about an embodiment of the present inventionin detail. The semiconductor device (STGJ) 11 having the structure shownin FIG. 3 was manufactured according to the processes shown in FIG. 4Ato FIG. 7B.

FIG. 10 shows an electrical characteristic of the semiconductor device(STGJ) 11. The transistor has a gate length of 45 nm, a gate width of220 nm, a thickness of the silicon layer of 20 nm, a gate insulatingfilm of 5 nm, a carrier density of 3×10¹⁸ cm⁻³ of the body regionforming the channel, a source and drain concentration of 2×10²⁰ cm⁻³,the reverse bias gate electrode of 1×10²⁰ cm⁻³. A vertical axis iselectric currents between a drain and a source, and a unit is alogarithmic expression expressed by ampere A. A horizontal axis is avoltage between a front gate and a source, and a unit is a linearexpression expressed by voltage V. The voltage of the back gate ischanged like −1.5V, −2.5V, 0V.

From a result shown in FIG. 10, it is found that leakage currents whenthe voltage between the front gate and the source is 0V are decreased,when a voltage is applied to the back gate in a backward direction of ap-n junction. Therefore, it is found to decrease leakage currents whenturning off a transistor, according to this structure.

As the first application, the semiconductor device of the presentinvention can be applied to integrated circuits that requires large ONcurrents, such as a power device, phase change random access memory(PRAM) and DRAM. Moreover, as the second application, the semiconductordevice of the present invention can be applied to ultrashort-channelvery-high-speed integrated circuits such as a super computer or CPUoperating at 10 to 100 GHz. Furthermore, as the third application, thesemiconductor device of the present invention can be applied tointegrated circuits that have the same characteristic as that on the SOIwafer excellent to thermal release characteristics like a conventionalbulk substrate which can respond to a cruel condition, such as anintegrated circuit for automotive engine control or an integratedcircuit for universe satellite. Moreover, as the fourth application, thesemiconductor device of the present invention can be preferably appliedto a low-cost transistor that has the same characteristic as that on theSOI wafer, in spite of not using a SOI wafer, an integrated circuitwhich utilizes sources for partial depletion type and complete depletiontype transistors that have the same characteristic as that on the SOIwafer, a floating-body-type transistor which is used in memory cells ofa capacitorless DRAM, and so on. In addition, as the fifth application,the semiconductor device of the present invention can be applied toreduction techniques of die square measure by three-dimension highintegration, such as LSI (ASIC), CPU, DSP for a low-cost specificationapplication that is determined by die square measure.

According to the above, it is possible to realize a characteristic equalto that of the SOI transistor at low cost without using an expensive SOIwafer and realize a transistor which can perform the reduction ofparasitic capacitance, the prevention of latch-up, the reduction ofjunction leakage, and the suppression of short channel effect. Since theSOI substrate is not used, it is possible to solve a problem of theself-heating effect owing to the large difference between heatconductivity of the embedded oxide film and heat conductivity of thesilicon layer. The semiconductor device becomes a vertical MOS structureusing a conventional substrate which can effectively release heatgenerated by the transistor similarly to the conventional substrate. Inaddition to this, when the semiconductor device is applied to a memorycell of DRAM, junction leakage currents can be reduced and refreshfrequency per time can be reduced. Moreover, the semiconductor devicebecomes a transistor structure on behalf of a planar-type transistorwhen the vertical MOS has a height similar to the width of theconventional planar-type gate. Short channel effect can be restrainedlike Fin FET and SGT by surrounding the whole channel region with thegate. A transistor with an extremely short channel can be manufacturedby dopant implantation in crystal growth in comparison with themanufacture by ion implantation. Moreover, a design of a transistorbecomes easy because the derivation of a depletion layer width of a p-njunction in a design can be also computed by step-type approximation.

According to the above, it is possible to realize a vertical MOStransistor with a long channel width in which ON currents can beimproved. A conventional SGT structure must set doping concentration ofthe source, the drain, the LDD, the pocket, and the body layer so thatthe threshold value is not changed in spite of the change of channellength. However, in the vertical MOS structure, since the thickness of asilicon layer is also related to the threshold value, the thickness ofsilicon layer must be held in order not to largely change the thresholdvalue in spite of the change of the thickness of the silicon layer. Forthis reason, it is preferable to have a structure that the silicon layerforming the channel has a cylindrical shape and a concentric crosssection. On the contrary, an arbitrary threshold voltage in the samechannel length can be realized by freely changing the thickness of thesilicon layer. For this purpose, although the conventional ionimplantation method requires a plurality of ion implantation processes,it can be realized by a single etching manufacturing process in thesemiconductor device.

Moreover, according to the semiconductor device of the embodiment, thecentral axis of the main pillar may be perpendicular to a surface of thesubstrate, and the source and drain diffused layers have a concentricshape centered on the central axis. In this way, since the thickness ofthe silicon layer is changed without changing the height of the mainpillar, it is possible to realize a vertical MOS transistor structurewith a stable width.

Moreover, according to the semiconductor device, the body layer has thesame concentric shape as that of the source and drain diffused layers,and thus the region in which a channel is formed becomes a concentricshape. Further, it is possible to enlarge the gate width of thetransistor without enlarging an outline dimension and thus increaseon-state currents.

Moreover, according to the semiconductor device, the main pillar has aconstant width in a transverse section thereof and has a constant heightin a longitudinal section thereof. In this way, it is possible to holdthe thickness of a silicon layer constant with a low-concentrationdoping and hold the threshold voltage constant. Furthermore, since theoutside diameter of the main pillar is increased while holding thethickness of a silicon layer constant, ON currents can be improved.

Moreover, according to the semiconductor device, the concentric shape ineach layer of the main pillar is a circle centered on the central axis.In doing so, it is possible to realize a structure by which a transistorbecomes a shape suitable for relaxation of electric fields and has achannel width capable of being easily increased. Compared to the SGTstructure, this structure can increase the outside diameter of thesilicon cylinder, that is to say, channel width while holding thethreshold voltage constant when the thickness of a silicon layer isconstant in a state that dopant concentration is constant. Therefore, ONcurrents can be improved. When the silicon layer forming the channel isformed in a concentric doughnut-shaped silicon cylinder with a longchannel width, an increase efficiency of ON currents per unit wafer areais higher than that of ON currents of SGT. The conventional SGTstructure has a complicated design in order to hold the same thresholdvoltage even if the silicon layer thickness and the channel width arechanged. For this reason, in order to obtain high ON currents per unitwafer area while holding a good transistor characteristic, it isnecessary to have a concentric doughnut-shaped structure with longchannel width like the semiconductor device of the present invention.Furthermore, high ON currents can be realized in the vertical MOStransistor. As a result, this results in a transistor structure suitablefor a memory cell such as a PRAM that requires large ON currents.

Moreover, the semiconductor device includes a back gate electrode thatis formed inside the main pillar, is connected with the source and draindiffused layers and the body layer in a p-n junction manner, and madefrom the second-conduction-type material. In this way, since the reversebias can be added through the back gate electrode made from thesecond-conduction-type material, the semiconductor device can functionlike a back gate of a conventional double gate by changing the thresholdvoltage without flowing electric currents even when a voltage is appliedto body layer. For this reason, it is possible to decrease leakagecurrents when turning off the transistor by dynamically raising orlowering the threshold voltage. However, it is necessary for the sourceand drain diffused layers and the body layer of this transistor to beformed of the first-conduction-type semiconductor. The reason is thatthe transistor becomes a bipolar transistor when the body layer is thesecond-conduction-type different from the first-conduction-type and thuselectric currents flow from the back gate electrode to the body layer.

Moreover, according to the semiconductor device, the front gateelectrode is arranged at an outer side of the main pillar, and the backgate electrode is formed in a pillar shape penetrating from the upperportion to the lower portion at an inner side of the main pillar. Thus,it is not necessary to provide a gate oxide film inward. In this way, itis possible to make a precision of a manufacturing process easy. Ingeneral, the inside and outside gate oxide films must have the sameoxide film thickness, in order to simultaneously operate internal andexternal gates. However, oxide films such as a thermal oxide film cannotrealistically have the same oxide film thickness because of reason ofthermal radiation. For this reason, it is preferable that the insidegate has a structure which does not depend on the film thickness of theoxide film. Here, the inside reverse bias junction gate dynamicallychanges a threshold voltage and the outside gate operates like the gateof the conventional transistor in a state that the inside and outsidegates have different gate structure. In this way, a high speed and lowpower consumption transistor can be realized as improved SGT. Asdescribed above, in the vertical transistor structure, it is preferableto form an inside gate structure that has a width in a process marginand can mitigate process precision.

Moreover, the semiconductor device includes a drawn electrode portionthat is drawn to the outer side than an outer circumferential face ofthe main pillar at a bottom of the lower portion of the source and draindiffused layers. In this way, the lower portion of the source and draindiffused layers can be formed to have a structure that largely protrudesin a transverse direction in comparison with the body layer and theupper portion of the source and drain diffused layers, and thus apoly-silicon wire can be easily performed. At this time, the front gateelectrode made from poly-silicon can be formed on a silicon oxideinsulating layer that functions as an etching stop layer. From aninfluence of parasitic capacitance or the like, since the width of thegate electrode parallel to the substrate is also the factor which isimportant to performance improvement, it is important to largelyseparate the source and drain diffused layers protruding from the bodylayer from the front gate electrode. In this manner, since the drawnelectrode portion is provided, the lower portion of the source and draindiffused layers can be lengthened in a direction perpendicular to thesubstrate and thus be largely separated from the front gate electrode.

Moreover, according to the semiconductor device, since a first wirewired to the front gate electrode and a second wire wired to the drawnelectrode portion are symmetrically arranged at the outer side of themain pillar, parasitic capacitance can be reduced.

Moreover, according to the semiconductor device, since a third wirewired to the upper portion of the source and drain diffused layers isarranged and formed at an upper side of the main pillar, the third wirecan be arranged at a position having small parasitic capacitance.

Moreover, the semiconductor device includes a plurality of back gateelectrodes that are respectively same as the back gate electrode and areprovided in parallel in a direction perpendicular to the outer surfaceof the main pillar, and capacitances that are provided between the backgate electrodes at the upper portion of the source and drain diffusedlayers. In this way, it is possible to realize a multivalued DRAM whichuses the plurality of gates from the single lower portion of the sourceand drain diffused layers.

Moreover, according to the method for manufacturing a semiconductordevice, since the outside diameter is increased while holding the samethreshold voltage, it is possible to realize a vertical MOS transistorwith long channel width in which ON currents can be improved. As setforth, the conventional SGT structure must set the doping concentrationof the source, the drain, the LDD, the pocket, and the body layer sothat the threshold value is not changed in spite of the change ofchannel length. However, in the vertical MOS structure, since thethickness of a silicon layer is also related to the threshold value, thethickness of the silicon layer must be held constant in order not tolargely change the threshold value in spite of the change of thethickness of the silicon layer. For this reason, it is preferable tohave a structure that the silicon layer forming the channel has acylindrical shape and a concentric cross section. On the other hand, anarbitrary threshold voltage in the same channel length can be realizedby freely changing the thickness of silicon layer. For this purpose,although the conventional ion implantation method requires a pluralityof ion implantation processes, it can be realized by a single etchingmanufacturing process in the semiconductor device.

Although the invention has been described above in connection withseveral preferred embodiments thereof, it will be appreciated by thoseskilled in the art that those embodiments are provided solely forillustrating the invention, and should not be relied upon to construethe appended claims in a limiting sense.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor pillar formed over a substrate; upper and lowersource-drain regions formed at upper and lower portions of saidsemiconductor pillar and made from a first-conductivity-type material; abody formed at an intermediate portion of said semiconductor pillarsandwiched between said upper and lower source-drain regions and madefrom said first-conductivity-type material, said body having a cavitytherein; and a front gate electrode formed on said body while placing agate insulating film therebetween.
 2. The semiconductor device accordingto claim 1, wherein said cavity has a cylindrical shape.
 3. Thesemiconductor device according to claim 1, wherein said cavity extendsinto said upper source-drain region.
 4. The semiconductor deviceaccording to claim 1, wherein said cavity extends into said lowersource-drain region.
 5. The semiconductor device according to claim 1,further comprising a conductive member formed on said upper source-drainregion, wherein a bottom surface of said conductive member is positionedlower than a topmost surface of said upper source-drain region.
 6. Thesemiconductor device according to claim 1, further comprising a backgate electrode formed in said cavity.
 7. The semiconductor deviceaccording to claim 1, further comprising a back gate electrode, saidbody being disposed between said back gate electrode and said front gateelectrode.
 8. The semiconductor device according to claim 1, whereinsaid cavity is filled with a second-conductivity-type material.
 9. Asemiconductor device comprising: a substrate; a body of a firstconductivity type formed over said substrate, said body comprising acylindrically shaped wall; an upper source-drain region of said firstconductivity type on an upper portion of said body; a lower source-drainregion of said first conductivity type directly beneath a lower portionof said body; a gate insulating film on said body; and a front gateelectrode on said gate insulating film.
 10. The semiconductor deviceaccording to claim 9, wherein said upper source-drain region comprises acylindrically shaped wall.
 11. The semiconductor device according toclaim 9, wherein said lower source-drain region comprises acylindrically shaped wall.
 12. The semiconductor device according toclaim 9, further comprising a conductive member formed on said uppersource-drain region.
 13. The semiconductor device according to claim 12,wherein a bottom surface of said conductive member is positioned lowerthan a topmost surface of said upper source-drain region.
 14. Thesemiconductor device according to claim 12, wherein said conductivemember is made of polycrystalline silicon.
 15. The semiconductor deviceaccording to claim 9, further comprising a back gate electrode formedinside said body.
 16. The semiconductor device according to claim 9,further comprising a back gate, said body being disposed between saidback gate electrode and said front gate electrode.
 17. The semiconductordevice according to claim 15, wherein said back gate electrode has a p-njunction with said body.
 18. A semiconductor device comprising: asemiconductor pillar formed over a substrate; upper and lowersource-drain regions formed at upper and lower portions of saidsemiconductor pillar and made from a first-conductivity-type material; abody formed at an intermediate portion of said semiconductor pillarsandwiched between said upper and lower source-drain regions and madefrom said first-conductivity-type material; a front gate electrodeformed on a outer surface of said body while placing a gate insulatingfilm therebetween; and a conductive member formed on said uppersource-drain region, wherein a bottom surface of said conductive memberis positioned lower than a topmost surface of said upper source-drainregion.
 19. The semiconductor device according to claim 18, wherein saidconductive member is made of polycrystalline silicon.
 20. Thesemiconductor device according to claim 18, further comprising a backgate electrode, said body being disposed between said back gateelectrode and said front gate electrode.